1. Field of the present invention
The present invention relates generally to TTL to CMOS input buffers, and more particularly to a buffer that maintains CMOS-type low quiescent current, even with typical TTL HIGH input levels, and yet is still able to reject high-frequency, high-amplitude noise.
2. Description of the Prior Art
Many electronic systems made today incorporate components that use more than one digital logic technology in their chips, microchips, integrated circuits (ICs), monolithic circuits, semiconductor devices, and microelectronic devices. For example, transistor-transistor logic (TTL) components and complementary metal oxide semiconductor (CMOS) components are typically combined in printed circuit board-level products. The two component types cannot be directly interfaced, because the TTL components use a bipolar transistor process and the CMOS components use a field effect transistor process. At a minimum, different switching thresholds and input and output characteristics create well-known inherent incompatibilities between bipolar and field effect transistors. Therefore, in order for a systems designer to drive a CMOS chip with a TTL chip, the CMOS chip must be able to accept standard TTL level signals.
The standard maximum TTL output voltage level to guarantee a logic "zero" is 0.4 volts, and the standard minimum output voltage level to guarantee a logic "one" is 2.4 volts. But in order to provide some design margin and noise immunity, a circuit which receives a TTL output must be able to recognize a logic zero as a voltage less than or equal to 0.8 volts. Similarly, the receiving circuit must recognize a logic one as a voltage greater than or equal to 2.0 volts. (The noise margin in this case is 400 millivolts.)
CMOS components switch their individual logic element outputs between ground and the positive supply voltage, effectively switching from "rail" to "rail". When CMOS and TTL chips are to be mixed, an interface circuit must ordinarily be provided to translate the standard TTL output voltage levels to voltage levels that can be used by a CMOS chip. For example, in a system where the positive supply voltage is nominally five volts, an signal input of 2.0 volts, or more, must be translated to a five volt signal level. And an input of 0.8 volts, or less, must be translated to zero volts. The interface circuit which accomplishes this task is generally referred to as a TTL-to-CMOS input buffer.
TTL-to-CMOS input buffers must accept a TTL "AC" input of zero to three volts and convert it to a CMOS output of zero to five volts, as fast as possible. According to standard TTL input specifications, this same buffer is required to recognize a TTL "DC" input of greater than 2.0 volts as a logic one, and a "DC" input of less than 0.8 volts as a logic zero. The simplest way to construct such a buffer is to use a CMOS inverter 12, as shown in FIG. 1A, wherein an N-channel transistor 14 and a P-channel transistor 6 are sized appropriately.
In typical CMOS processes, the N-channel threshold voltage will be about 0.8 volts, and the P-channel threshold voltage will be about -1.1 volts. Since N-channel transistor gain is about twice that of P-channel transistor gain, per unit of area, it has been common to implement the input buffer of FIG. 1A by making the width-to-length ratio (W/L) of the N-channel transistors, such as transistor 14, about four times the W/L of the P-channel transistor, such as transistor 16, in order to produce a TTL-to-CMOS input buffer 12 with the desired electrical characteristics. These ratios are designed to make an inverter that actually switches when its input voltage is about 1.4 volts. (This voltage is typically labelled Vin.) The switching point is halfway between the standard TTL LOW (0.8 volts) and TTL HIGH (2.0 volts).
For inverter 12, when Vin is less than 0.8 volts, N-channel transistor 14 will be completely turned off, because its gate-to-source voltage (Vgs) is less than the N-channel transistor threshold voltage (Vtn). And P-channel transistor 16 will be turned on, because its Vgs will be less than -4.2 volts. With N channel transistor 14 turned off and P-channel transistor 16 turned on, the inverter output node is pulled substantially to Vcc (which is nominally at +5 volts). The DC current drawn from Vcc in this case will be very small (e.g. just leakage).
MOS transistor gain .beta., can be described as ##EQU1## so when, in FIG. 1A, Vin=2.0 volts, N-channel transistor 14 will be turned on, because it has a Vgs&gt;Vtn. P-channel transistor 16 will also be turned on, because its Vgs=-3.0 volts. See FIG. 1B. However, N-channel transistor 14 has a lower effective on-resistance (Ron) than does P-channel transistor 16. This is generally due to, ##EQU2## which is sized larger than ##EQU3## and
b) N-channel transistor 14 having an inherently greater Carrier mobility .mu., thus making the gain of N-Channel transistor 14 greater than that of P-channel transistor 16.
The lower on-resistance of N-channel transistor 14 results in Vout being less than 0.8 volts, which is a logic zero. The problem with a logic one input of two volts is that neither P-channel transistor 16 nor N-channel transistor 14 are completely turned off, which allows a significant DC current to be drawn from Vcc. This current is a function of the actual transistor sizes, it can typically range from as little as 0.1 mA to over one milliamp.
For circuits with many TTL-to-CMOS input buffers, the cumulative standby current for TTL logic one inputs can be significant. Such a standby current can generate extra heat which must be dissipated, and creates an additional burden for the system cooling scheme (whether it be a fan or convection air flow). This standby current is obviously particularly undesirable if the system is powered by batteries. Another problem created by this standby current is faced not by the system designer, but by the chip designer. The physical size of the internal power buses of the chip must be made larger to accommodate this current, which wastes chip real estate.
There have been several circuits proposed which are more complex than the circuit of FIG. 1A aimed at reducing the above standby current for a TTL logic one input. However none totally reduce the DC current to just leakage. A TTL-to-CMOS input buffer is offered by Noufer, et al., in U.S. Pat. No. 4,471,242. His input buffer translates TTL levels into CMOS levels while eliminating the DC current path in prior art input buffers, such as shown in FIG. 1A. Noufer, et al., introduce a reference voltage to match the lowest level of a TTL logic one signal. The input inverter has a P-channel transistor which does not turn on when the TTL signal is at the lowest level of a logic one, by having a source at the reference voltage. This reference voltage is selected to be less than the lowest level of a logic one minus the threshold voltage of the P-channel transistor. However, Noufer, et al., do not teach the use of a CMOS NOR gate which provides feedback through a P-channel transistor to its cross-coupled inverters. Worse, the reference voltage generator draws current in Noufer, et al.